1. Field of the Invention
The present invention relates to laminated ceramic capacitors, and in particular, relates to technologies of laminated ceramic capacitors of which structural defects such as cracks generated during firing while the laminated ceramic capacitors are produced or structural defects caused by electrostriction (inverse piezoelectric effect) can be controlled or prevented.
2. Description of the Related Art
As shown in FIG. 11, a typical laminated ceramic capacitor includes a plurality of inner electrode layers 53a and 53b that oppose each other with ceramic layers (dielectric layers) 52 disposed therebetween and a pair of outer electrodes 55a and 55b disposed at end surfaces 54a and 54b, respectively, of a ceramic element 51. Ends of the inner electrode layers 53a and 53b are alternately extended to the corresponding end surfaces so as to be electrically connected to the outer electrodes 55a and 55b, respectively.
When a dielectric with a high dielectric constant is used in such a laminated ceramic capacitor, stress is imposed on the ceramic dielectric layers due to electrostriction (inverse piezoelectric effect) that causes mechanical displacement by voltage. Furthermore, when the number of lamination layers constituted by the ceramic dielectric layers and the inner electrode layers is increased so that the capacity is increased, stress imposed on the entire laminated ceramic capacitor is increased. This leads to crack generation and a reduction in breakdown voltage or withstand voltage.
To solve this problem, as shown in FIG. 12, a laminated ceramic capacitor having an intermediate layer 62 being disposed between capacitance forming layers 61a and 61b for relieving stress caused by the inverse piezoelectric effect has been proposed so that breakdown voltage or withstand voltage does not drop to a lower value even when the number of lamination layers constituted by the ceramic dielectric layers and the inner electrode layers is increased (see Japanese Unexamined Patent Application Publication No. 9-180956). The capacitance forming layers 61a and 61b each have a lamination of the ceramic layers (dielectric layers) 52 and the inner electrode layers (capacitance-forming inner electrode layers) 53a and 53b that contribute to the formation of electrostatic capacitance.
In FIG. 12, components having the same reference numbers and symbols as shown in FIG. 11 indicate the same or corresponding components.
The capacitance forming layers having the inner electrode layers greatly contract during firing. On the other hand, the contraction rate of the intermediate layer 62 having no inner electrode layers is smaller than that of the capacitance forming layers. Therefore, when the thickness of the intermediate layer 62 having no inner electrode layers is too large in the above-described known laminated ceramic capacitor, stress becomes concentrated in the intermediate layer during firing, and causes, for example, a crack C in the intermediate layer 62 as shown in FIG. 13.
Since the thickness of the intermediate layer needs to be set such that crack generation in the intermediate layer due to contraction difference during firing is prevented while crack generation caused by electrostriction (inverse piezoelectric effect) is prevented, design flexibility is disadvantageously reduced.
In order to relieve the contraction difference generated between the capacitance forming layers having the inner electrode layers and the intermediate layer having no inner electrode layers during firing, additional inner electrode layers can be provided for the intermediate layer. A configuration having an intermediate layer including inner electrode layers that do not form capacitance is also described in Japanese Unexamined Patent Application Publication No. 9-180956.
However, the structure and the arrangement of the inner electrode layers need to be appropriately adjusted so as to effectively relieve the contraction difference generated between the capacitance forming layers and the intermediate layer, and desired effects are not easily produced in reality.
For example, when inner electrode layers forming no capacitance and divided into four parts are arranged in a single layer (in the same plane) as shown in FIG. 4 in Japanese Unexamined Patent Application Publication No. 9-180956, cracks are generated during heat treatment as described in the following explanations of preferred embodiments of the present invention.